1. Field of the Invention
The invention relates to the field of MOS processing.
2. Prior Art
In the fabrication of large scale integrated MOS circuits it is often desirable to have devices (such as field-effect transistors) of different thresholds on the same substrate. One example where devices of different voltage thresholds are employed on a common substrate is the combination of depletion mode field-effect transistors and enhancement mode field-effect transistors. To fabricate these devices on a common substrate typically a separate masking step is employed to isolate the channel regions of the depletion mode devices. Then an appropriate dopant is diffused into the substrate. Following this the enhancement mode devices and depletion mode devices are simultaneously fabricated on the substrate.
It is useful in some applications to employ depletion mode and enhancement mode devices of different thresholds on the same substrate. A choice of voltage thresholds permits optimization of designs. However, if a separate masking step is required for each such threshold, fabrication considerations such as yield, make the use of different threshold devices less practical. With the present invention a plurality of host regions of different conductivity types and dopant concentration levels are formed, without the need for a separate masking step for each host region.